In T-topology, the clock traces need to be routed with a prolonged delay than the strobe traces per byte lane. Insertion Loss. 8pF per cm ˜ 10nH and 2. 1. This is where the TDR (time-domain reflectometer) noted in Part 1 of this article comes. Optimization results for example 2. 9 470 2665. Therefore, you should make the 50Ω impedance traces 5. Copper area has. Make trace widths appropriate for the current load. Where: Z0 Z 0 = characteristic impedance of the asymmetric stripline in ohms (Ω). A PCB trace is a highly conductive track that is used to connect components on a printed circuit board. PCB manufacturer generally verifies the impedances with impedance coupon (traces drown during design in a separate portion outside our required size of the board) during PCB manufacturing process. 031”) trace on 0. 024 for internal conductors and 0. It is typically utilized in multi-layer PCB designs, where the signal trace is sandwiched between two ground planes. Figure 1 shows a simple example of insertion loss for a 16-inch trace across different PCB materials at both 16 GT/s (8 GHz Nyquist) and 32 GT/s (16 GHz Nyquist) data rates. Delay Tune sawtooth, accordion and trombone types. Delay constant of a microstrip line. 6 . 03 ns/m). For example, if you require a 5mil trace to achieve 50Ω impedance and if you have also routed other signals with 5mils width, it will be impossible for the PCB manufacturer to determine which ones are the controlled impedance traces. 0 dielectric would have a delay of ~270 ps. 031”) thick PCB (FR-4) has: ˜ 4nH and 0. 515 nsec. Source Termination. 8 mm 0. It is one of the most crucial factors that should be calculated and analyzed when designing a PCB. DLY is a standard parameter associated with PCBs. Brad 165. Before selecting the high-speed PCB material for your fast PCB plan, it is essential to decide a worth (or qualities) for DK and Z0 for your transmission line (or lines). Those familiar with high-speed design know that trace geometry, trace location, and board substrate all affect signal speed, impedance matching, and propagation delay. So (40%) for a 5 mil trace. a. Designers need numerical tools and the correct analytical formulas to calculate the inductance of their PCB. 11:10, and 9:8. Clearly a corner causes reflections. And you need to dump heat THRU the FR-4 epoxy fiberglass substrate, to move heat into the plane. Assume trace delay, pin capacitance, and rise/fall time differences between data and clock are negligible. 2 volts (per DIMM) instead of the 1. Refer to PCB design requirements or schematics. Use the following equation to calculate the stripline trace layout propagation delay. I've read that you want to keep intra-pair trace length to 5mils max and that inter-pair trace length matching is not terribly important. in common use is to allow 7,500 to 10,000 volts, dc per inch in air. 126 x 0. The aim is to demonstrate a practical way of performing. Use the following equation to calculate the stripline trace layout propagation delay. 3. 8mm (0. Then, just apply: Allowed_Length = Allowed_Delay/(140 ps/inch) where 140 ps/inch is. 4. To maintain trace impedance, the width of the trace should be modified when changing from one board layerThe formula for the nominal DC resistance of a rectangular pcb trace is given in [2. Signal skew occurs in a group of signals when there are delay mismatches. 8mm or smaller ball pitch is recommended for 224G PAM4. The propagation delay is expressed in time per unit length. PROP_DELAY 16281-005 Figure 5. The coax is a good way to create a transmission line. designning+b46 controlled impedance traces on pcbs 12. (Less than 2 ns) Most important is to match and. As an example, Zo is 20 millohms. Varies between PCB’s. 2 PCB Stack-up and Trace Impedance. The thermal resistance of this foil is also 70 degree Centigrade per square, ignoring the holes and the etched gaps between the squares. . 2 mm trace matching requirement. 7563 mm (~30 mils). Maximum current flow is going to be 12 Amps RMS. Stripline Layout Propagation Delay. If. 1 dB/inch/GHz for a low loss channel. To optimize the PCB trace impedance and stackup, you must follow the key notes below: If thin dielectric layers with high dielectric constant (Dk) cannot be. Most of this time is taken up by the edge rate of the driver. 0 electrical specification 2. 0 and frequencies up to 20 GHz. g. D = delay in ps/inch The delay of FR4 material is 180 ps/inch. Use equation 1 to calculate propagation delay (tpd). 1. those available. 2. 015) , the loss is dominated by the square root function at low frequencies, then becomes dominated by the linear dielectric loss at higher frequencies, as seen in. There are many calculators available online, as well as built into your PCB design software. 024 x dT0. 51 The propagation delay on a PCB trace is the one-way (source to load) time required by a signal to travel to reach its destination. e. . Measurements of S-parameters. PCB Post-Layout Simulation Phase. More exotic dielectrics (like teflon, etc) can be quite different. Regards, The term “transmission line” refers to the behavior of a trace on a PCB rather than its construction. If there are 3 CK trace delay cells and you only want to use 2, choose one of the actual trace delay values from the two cells and copy it into the 3rd cell. Differential Signal Pair -Stubs • PCB trace lengths should be kept as short as possible. 25 to 0. Especially when creating a model for the transmission line in a simulation tool. So (40%) for a 5 mil trace. To achieve this, you may have to put small sections of trace tuning into the shorter line to equalize them. The rule of thumb is to be cautious when the edge rate is less than ⅙ of the propagation delay on the length of the copper trace. They all have different frequencies of response (ranges are approximate): • 0 to approximately 30 KHz -Power supply response (varies considerably) • 70 Hz - approximately 40 KHz Bulk power supply capacitors (works with. 1. A ballpark figure for a PCB trace is about c/1. 0 dielectric would have a delay of ~270 ps. 0pF per inch The current-handling capacity of a PCB depends on various factors, including trace width, thickness, material, and temperature rise. Find the trace delay, or “DLY,” in pico seconds or “ps” per inch. The IPC-2141 trace Impedance calculator will help make initial design easier by allowing the user to input basic parameters and get a calculated impedance according to the IPC-2141 standard. 8. A PCB transmission line is a type of interconnection used for moving signals from the transmitters to the receivers on a circuit board. pd] = 1/V (2a) where * V is the signal speed in the transmission line. Time Delay (ps) Inspector Adolph Judgement PASS Fail Wait MRB-A-_____ Approval Alex Testing Date 2020/11/11 MFG Date Code xxxx Timing Delay Spec. 08 cm) PCB loss. The PCB stack-up configuration determines several elements of the design: • Number of layers available for routing • Number of layers available for power and ground planes • Single-ended trace impedance, capacitance per inch and propagation delay per inch of a. 36 RF / Microwave Design - Line Types and Impedance (Zo) Coplanar Waveguide)CPW Allows Variation of Trace. Working with the right design software can help you comply with basic LVDS PCB layout guidelines and LVDS routing guidelines that are needed for signal integrity. 81 cm. For FR4, using effective epsilon of 3. The skew can be introduced with additional PCB trace delay on the carrier board or by adjusting the internal delay settings at the phy or processor. Due to the variations of material from which an FRC4 board can be fabricated, this. the max delay of STARTUP), the min delay of data, and the board routing delayI have done the impedance calculations to figure out the track geometry needed for 100 ohm differential impedance and confirmed it with the board house. There are many tools available to calculate the trace impedance on high speed traces. 64 inches on the surface of the PCB for this specific material to not be considered high-speed. The DATA1 PCB delay is 0. In lower speed or lower frequency devices,. The calculator is set up to handle an asymmetric arrangement, where traces are not centrally located in the PCB layer stack. Subtract the DUT1 PCB-run delay of 0. 7E-6 ohm-cm. In vacuum or air, it equals 85 picoseconds/inch (ps/in). 071 inch Model 636 SMT General Purpose Clock. 40 some pros and cons of embedding traces 12. For a microstrip trace exposed to air on one side, the delay in FR-4 is a little bit less (about 140 ps/inch). This tool calculates the time delay in inches per nanosecond. the frequency as 10 GHz, the surface roughness as 6 μm, and the length of the trace as 1 inch. 8. • We obtained this by assuming the signal paths were ideal. If you have an edge rate of 1ns and the copper trace is longer than 1 inch, you’ll need to take appropriate measures for impedance control. Conductor loss in a PCB transmission line. 5. The trace width can then be calculated by re-arranging this formula to determine the cross-sectional area that. First choice: Don't. In this example, the delay difference between the P and N legs as well as the measured trace lengths end-to-end are the same in the layout tool. In vacuum/air, it’s equal to 85ps/in. Trace LengthTrace Length §Longer trace length ⇒ loss ↑ ü~0. Trace length greatly affects the loss and jitter budgets of the interconnection. A given trace may behave as a transmission line under some conditions while behaving as a simple conductor in other conditions. The PCB delay is half of this, or 1ns. 695 nsec—half the second-step measurement of 1. 031”) trace on 0. What is the voltage at source at. With a 0. Frequency: Frequency at which the stripline is analyzed or. The reason for length matching in this case is because of TIMING. Now let us look a bit more in detail into the two types of traces and geometry assumptions. 5 = 2 inches need to be designed as. So if you have 1 logic level then you'll have 2 routes (one to the gate, one from the gate). Brad - November 15, 2007 Mike, In PCB Designs we use another term propogation speed and measure it in terms of picosecond per inch. Perhaps the most common type of transmission line is the coax. When using internal clock skew control, the TX and RX traces should be independently matched in length to within one inch (approximately 25 mm). 0 ns Output minimum delay = –t h of external register = –0. (For purposes of this explanation, CMOS receivers look like very small capacitors that can be considered to be open circuits. The PCB shown in Figure 2 was design to evaluate the effects of only two corners per trace using various. So if you then need to do a, for example 100ps delay on a trace with a Tpd factor of 170ps/inch (a quite common PCB velocity factor) the trace would be ~590 mils in length. After the TRL cali-. 81 cm) to 2 inch (5. 1 ns Using Equation 1 through Equation 4 we can calculate the margin of the setup and hold time with the selected ID and PCB skew. As those do not need to be accurate to the picosecond, I'm looking for generally accepted rules of the thumb rather than exact formulas. The nice part about coax is that it can be bent and flexible unlike most pcb transmission lines. 32 f \ tan(\delta) \sqrt{\epsilon_r}\] Equation 1. Varies between PCB’s. Actual data vs 1X AFRHere are some of the best practices I find for trace routing: Verify your manufacturer's limits for trace width and spacing before you start routing. 8 core of FR4 material, we would have a propagation delay of approximately 150 ps/inch, or approximately 6 inches/ns. PCB traces. Balancing FR4 dielectric constant with PCB laminate thickness and trace width is a difficult problem, but the right stackup manager can help you produce accurate impedance and propagation delay calculations. 06 meters. 8dB/inch o Skip-layer STL: 1. 8 CoreSight™ ETM Trace Port Connections. 39 nsec. So the board thickness variation causes the calculated trace impedance to vary more than the wildly variable Er values that are commonly quoted. 5 dB 14-inch on low-loss PCB material Up to 0. The rule of thumb is to be cautious when the edge rate is less than ⅙ of the propagation delay on the length of the copper trace. 046The ability to analyze and predict the current/temperature effects of isolated traces is helpful, but the actual temperature of a trace may be different because of uncertainties in the actual trace thickness or board material thermal conductivity coefficient. Capacitance per unit length is proportional to trace width (neglecting edge effects). The designer needs to confirm the RF Trace’s width/spacing to adjacent layer GND (as per 50E/chipset recommendation/ RF antenna. • Signal traces should not be run such that they cross a plane split. If you are using some form of delay line to match clock delays at all points of usage within a pc board, here's a short list of the items you need to match: Trace length, Trace configuration (microstrip or stripline, to match the delay per inch), Trace width and impedance (to match high-frequency losses),the smaller the group delay variation hence the less dispersion (ISI). PCB trace thickness is an essential parameter in PCB designs, and it is often determined by the manufacturer. These delay lines are available with or without. 37 mil), the deviation of the calculated results from results obtained using XFX, a 2D numerical field solver from Innoveda, is listed below:%PDF-1. To view the matching requirements (including derating values), please refer to the DDR3 Design. An important component of any layout is determining what PCB stack-up to use. R is the series resistance per unit length (Ω/m) L is the series inductance (H/m). The inductance of a PCB trace determines the strength of any crosstalk it will receive. Ideally, this trace width to height above the ground plane ratio is between 1: 1 and 3:1. 49 references 12. (138 pF/m) yields 178. Figure 2 Test PCB and TDR response. 在can总线应用中，pcb走线起着至关重要的作用。因为pcb走线可以影响总线的可靠性、传输速度和抗干扰能力等方面。因此，设计一个良好的can总线pcb走线布局非常重要。 首先，在设计can总线pcb走线时，需要满足一定的布局规范。如在布局过程中应遵循短连、粗连. The PCB internal/external trace resistance shall be calculated according to the following formula: R = (ρ * L / (T * W)) * (1 + α * (TAMB – 25 °C)) Where: R is the trace resistance [Ω] ρ is the resistivity parameter, whose value for copper is 1. Sample 4-Layer PCB StackupFind the trace delay, or "DLY," in pico seconds or "ps" per inch. Typical Lumped Parameters Capacitance - A narrow trace has a capaci-tance of 2 pF per inch (0. 5. 1 Flight Delay and Skew Advantages to Specifying Timing Specifications via PCB Routing Rules Another particularly nasty negative result is one which reflects that the system designer's attempt was to design an. Microstrip Trace Impedance with Changing Trace Width Z0 = 87 εr + 1. If you must turn a corner with a signal trace, the trace should bend by no more than 45 degrees. 39 symmetric stripline pcb transmission lines 12. This gives us a delay of 176 ps/inch for a typical FR-4 stripline. Capacitance = ϵ ∗ Area/DielectricThickness C a p a c i t a n c e = ϵ ∗ A r e a / D i e l e c t r i c T h i c k n e s s. FR4 PCB is typically 4 to 4. PCB traces can be particularly troublesome. 2. If you use a different transmission line calculator, for example the Saturn PCB one, or this online one, they. Height: Height of the substrate. Let’s calculate the propagation delay using trace length and vice-versa. A typical value for a 50 Ohm microstrip is ~150 ps/inch, and for striplines a typical value is ~171 ps/inch; both assume. The electric signals in PCB traces travel at a smaller speed. Microstrip construction consists of aA bit new to PCB design, I have to run two traces between two pins, and the best way I can think of is to have one trace go to the bottom layer through a via and then run directly under the top layer trace. I am given the equation for parasitic-capacitance as: C = ϵr ⋅ϵ0 ⋅ L ⋅ W d C = ϵ r ⋅ ϵ 0 ⋅ L ⋅ W d. This gives an inductance of 9. With over 300 calculators covering finance, health, science, mathematics, and more, GEG Calculators provides users with accurate and convenient tools for everyday calculations. A PCB design package that incorporates a propagation delay calculator as part of your design rules makes it easy to compensate for propagation delay, allowing. In a vacuum or through the air, it equals 85 picoseconds/inch (ps/in). On PCB transmission lines, tpd is given by: Propagation delay in PCB transmission lines For example, a 1-inch trace can introduce an approximate 5. 018 Standard FR4. 2 Find the trace delay, or "DLY," in pico seconds or "ps" per inch. Where T is the board thickness and H is the separation between traces. To a 2-ns rise time, this is an impedance of 15 Ω. The PCB traces act as transmission lines when the line delay is equal to or greater than 1/6 the rise (or fall) time. Vis the signal speed in the transmission line. = 1. 33 ns /meter. With a 0. Length-Matching All Traces - match all RX traces to each other, and match all TX traces to each other. 01 is. If you obtain component models from your manufacturer, the IBIS 6 documentation for the particular component should include the pin-package delay. 1nS of propagation delay is added to a signal for every 150mm / 6″ of PCB trace. xxx Differential Pair Spec. Brad 165. In the pair with smaller spacing (5 mil), the small traces in our 21 mil amplitude length tuning section have odd-mode impedance of 58. 1 mm bit, a minimum clearance of 0. 048 for external conductors. The SPI master module creates a SPI clock of 20 MHz which is only active while communication is ongoing. 92445. 0pF per inchHow to calculate trace delay? Simple (not recommended): Measure the physical trace length (in mils or mm) in a layout tool. Using the above rule strictly, termination would be appropriate whenever the signal rise time is < ~500 ps. The calculated FPGA and HardCopy ASIC timing constraints are as follows: Output maximum delay = t su of external register = 1. PCB Trace 100 Ω Differential Impedance Source SCOPE CAT5 Belden MediaTwist(tm) Figure 1. Z. Dielectric constant. 4 ‘Excessive’ Output Delay If the total load capacitance is excessive there is no guarantee for the operation of the device. For buried traces, such as stripline traces, the return path conductor might actually be two planes, one above, and one below. Remember, 100+ MHz digital logic carries 1GHz components too, because square. THESE FORMULAS ARE APPROXIMATIONS! They should not be used when a high degree of accuracy is required. 8-4. As you’re probably aware, signals travel on PCB traces with a certain speed. At very low frequencies – until about 1MHz, we can assume that the entire conductor participates in the signal current and hence Rsig is the same as the ‘alfa’ C resistance of the signal trace, which is: Where: ρ = Copper resistivity in ohm-inch . gradual. A more convenient unit for propagation delay for PCB designers is picoseconds per inches. Minimum CAN Device Spacing Load capacitance includes contributions from the CAN transceiver bus pins, connector contacts, printed-circuit board traces, protection devices, and any other physical connections as long as theCable/PCB trace 5 Delay per meter. Component: Copper Traces Purpose: Interconnect two or more points Problem: Inductance and Capacitance x = length of trace (cm) w = width of trace (cm) h = height of trace (cm) t = thickness of trace (cm) e r = PCB Permeability 0. To ensure timing alignment for all channels per port, both the substrate trace length plus the PCB trace length for each signal must be matched to meet the trace length skew tolerance for all signals within the clock domain. For 12G-SDI cable driver applications where the output rise/fall times must be less than 45 ps, this means that each inch of FR4 trace can decrease margin from the limit by about 5%!Cable/PCB trace 5 Delay per meter. 5 ps/mm and the dielectric constant is 3. data rate approaches ~10 gigabits per second on traces with routing lengths often greater than 12 inches in today’sIPC-2152 Calculator. Stripline Layout Propagation Delay. 75. PCB Trace Attenuation Comparison per 1 inch Trace Length for various dielectric materials, while Trace Width is 5 mil, results up to 20 GHz. A printed circuit board (PCB), also called printed wiring board (PWB), is a medium. For Example. 8pF per cm ˜ 10nH and 2. The tolerance on a trace width might be +/- 2 mils. As can be seen, the dielectric loss is directly determined by the dielectric constant and loss tangent of the material. 33x10-9 seconds /meter or 3. A better geometry would be something a 50 mil x 50 mil square. To calculate PCB trace resistance, The 50 ohm PCB trace calculator is designed considering the following formula. trace in Megtron 6 with HVLP laminate shows about 20 dB less loss when compared to similar trace in FR-4 board. • When the design is laid out the ideal signals become PCB traces. 0 16 GT/s 28. 433: 107893,50. Figure 7. So worst case 5. Assuming the delay time of a transmission line as shown in . On typical PCB material we get the rule of thumb values at Er=4, we have about ~15cm/ns or ~169ps/inch. A 0. 0 x 5. GEG Calculators is a comprehensive online platform that offers a wide range of calculators to cater to various needs. CBTL04083A/B also brings in extra insertion loss to the system. Ohm’s Law provides the framework for solving network analysis problems; when the curtain gets pulled back, Ohm’s Law updates to become the relationship between voltage, current, and impedance, not resistance. As an example, the skin depth in a copper conductor at 1 GHz is 2. Dispersion is sometimes overlooked for a number of reasons. In terms of maximum trace length vs. This calculator determines the impedance of a symmetric differential stripline pair. 1. Keep the spacing between the pair consistent. 5 ohms peak to peak. 5 ps/mm and the dielectric constant is 3. inductance scales by length, capacitance by area. The parasitic inductance that resides along a PCB trace increases the impact of any voltage spike induced by switching power supplies. 7. 4 Advantages to Specifying Timing Specifications via PCB Routing Rules 5 Solutions to High-Speed Design Issues 5. 5 ps longer than the N leg delay at the Nyquist frequency (12. g. PCB Trace Impedance Calculator; microstrip; Electromagnetic Compatibility Laboratory. Approximations for the impedance, delay, inductance, and capacitance of. Keep traces short and direct, which is easiest. 1 inches, with a crystal mounting pad of about 0. Designers need numerical tools and the correct analytical formulas to calculate the inductance of their PCB. These traces can be made of materials, typically copper, and are designed to have specific widths and thicknesses to handle different current loads. Because both signals are differential, you can take the average of DDR_CK and DDR_CKn (or DDR_DQS and DDR_DQSn) and input the length (in inches) for each byte in each cell. The IPC-2222 standard specifies minimum hole diameters for plated through-hole vias for different classes of vias as follows: Minimum hole size = Maximum lead diameter + 0. Now also calculates DC resistance with temperature compensation. The finalPropagation delay is how long it takes a signal to travel over a network from its sender to its receiver. Where, Area = Thickness*Width. Microstrip construction consists of a• PCB traces and planes to and from all of the above All of these elements play a part in the effectiveness of the PDN. Zo of the transmission line). The design guide has an excel spreadsheet to help with max trace length and button dia requirements. Many things might go wrong if these parameters are not carefully chosen. 2. There is tolerance in the dielectric constant in FR4. 2 inch or more, the signal will have a severe ringing. 9 I have to interface a video format converter with a ADC IC, which converters RGB analog data to digital. power dissipation: lower resistance reduces the RC time constant but increases the amount of current that flows from V DD to ground (through the pull-up resistor) whenever SCL or SDA is logic low. There are some advantages to using a microstrip transmission line over other alternatives. If you use a different transmission line calculator, for example the Saturn PCB one, or this online one, they. Speci-mens from 3. 3. The term “transmission line” refers to the behavior of a trace on a PCB rather than its construction. When do PCB traces need impedance matching? Impedance matching is decided by the steepness and the rise/fall time of the signal rather than the frequency. Then, just apply: Allowed_Length = Allowed_Delay/(140 ps/inch) where 140 ps/inch is typical for a microstrip on FR4. You then subtract the PCB-trace delay of DATA1 from the total delay to get 3. e. A PCB transmission line is a type of interconnection used for moving signals from the transmitters to the receivers on a circuit board. PCIe®Generations Data Rate Total Budget Add in Card Budget Reach Goal PCIe®3. PCB-RULER-ND: Metric Side Rev 1 (March 2016) 12 inch (~30. The spacing between traces is 45nm as well (and the thickness of the metal layer is 45nm). an inch of #20AWG wire has about 20nH of inductance an inch of 0. The thick. 9E-3 ohm/ohm/C. Component: Copper Traces Purpose: Interconnect two or more points Problem: Inductance and Capacitance x = length of trace (cm) w = width of trace (cm) h = height of trace (cm) t = thickness of trace (cm) e r = PCB Permeability 0. The EZ5 material measured at 54% of the baseline material, A1X. The copper weight is measured in ounces per. 29 4 Feature-Specific Design Information. Here is how we can calculate the propagation delay from the trace length and vice versa: [t. Figure 1. Edges of Trace and Grounds). The tolerance on a trace width might be +/- 2 mils. Altium Designer ® includes layout tools and an advanced layer stack manager, giving you full control over all aspects of your design. The propagation delay corresponding to the speed of light in vacuum is 84. 725. 5 ns. The stitching Via Style can be configured manually or imported from the applicable Routing Via Style design rule by clicking the Load values from Routing Via Style Rule button. This length conversion calculator converts metric and imperial units including kilometers, meters, centimeters, millimeters, miles, yards, feet, and inches. Ordinary logic gate (each) 100 “10,000. On PCB transmission lines, the propagation delay is given by: Case study: Calculating trace length on a PCB In the context of FPGA design, I sometimes need to estimate PCB trace delays between the FPGA and external devices to properly constrain the input/output timing. Looking at laying out a PCB that will utilize PCIE. 5. Propagation Delay The propagation delay of the signal is the time it takes for the signal to travel a specific distance. I have a design that communicates to multiple SPI devices. Enter delays inside the whitespaces only. delay of the PCB track is equal to or greater than one-half the applied signal rise/fall time (whichever edge is faster). Total loop inductance/length in 50 Ohm transmission lines. light travels at 299,792,458 meters per second (m/s). The PCB trace may introduce 1 ps to 5 ps of jitter and 0. The microstrip is a very simple yet useful way to create a transmission line with a PCB. So it should be possible for the velocity to change without the characteristic impedance changing, but. Two very important properties of a transmission line are its characteristic impedance and its propagation delay per unit length. Typical Lumped Parameters Capacitance - A narrow trace has a capaci-tance of 2 pF per inch (0. However, there are techniques to reduce the spacing for both dc and ac. The delay per unit length in your PCB is dependent on the material that is used and can have a wide range (150-185 ps/inch is typical). Managing all of these can be done manually. 25 to be valid. Figure 5-1 shows an example PCB stackup with trace routing on layer 1, ground on layer 2, power on layer 3 and trace routing on layer 4. Explore Solutions. Simple - Via Style(Hole size and diameter) is the same through all layers. Just check signal quality after assembling first board to be sure that it's ok. Why FR4 Dispersion Matters. Each end of a differential pair. 030 trace has 10nH and a sq inch of FR-4 has about 5pF of capacitance. The next equation shows the amount of inductance in microhenries for a component lead that has a diameter of 0. The PCB traces act as transmission lines when the line delay is equal to or greater than 1/6 the rise (or fall) time. Delay probability density is then evaluated assuming the uniform distribution of the trace offsets.