Via stitching spacing calculator. Modified 5 years, 8 months ago. Via stitching spacing calculator

 
  Modified 5 years, 8 months agoVia stitching spacing calculator Just focus on getting the correct amount of stitches

The first step is to determine the length of your cast-on stitches by calculating a ratio to the number of stitches in the original pattern gauge divided by 4 inches to the number of cast-on stitches the pattern calls for divided by X or the length you’re trying to find. These PCB vias will have a pad on each layer where a connection is a made to a trace. 2. 0. 6 GHz bandwidth. Via shielding (sometimes called a picket fence) is where one or two rows of vias connect copper pour together at the perimeter of some tracks or the copper pour areas. Visit the cement calculator to determine how much cement, sand, gravel, water, or money you'll need for this concrete volume. A variant of coplanar waveguide is formed when a ground plane is provided on the opposite side of the dielectric, which is called finite ground-plane coplanar waveguide (FGCPW), or more simply, grounded coplanar waveguide (GCPW). for bracing, what criteria are used to design the stitch plate and its connection to the angles? AISC Specification (ANSI/AISC 360-10), Section E6. And I can tell you: If that works and really does something measurably good in a predictable way, there will be plenty of solid science to back it. . Actual results may vary depending on application and conditions. 25% MIN OF THE JOINT SHALL BE WELDED. Spacing Increases and Decreases Evenly Across a Row or Round. Rarer but still common is via stitching. With a single line of topstitching or edgestitching, stop at the corner with your the the down position, and pivot. The On Center Spacing calculator computes the even spacing between a number (n) of objects (e. RF Via fences/stitching spacingHelpful? Please support me on Patreon: thanks & praise to God, and with thanks to t. Satin Spacing Space Settings. Try For Free Buy Now PCB via stitching and shielding Via stitching on the PCB is where a large number of vias are used to connect copper areas on different layers together. All of the above is great for validating your via spacing decisions. Some people recommend 0. Stitching Vias 3 High-Speed Differential Signal Routing 3. The box ‘Automatic’ with Satin Spacing is activated, which means that V8 will calculate the number of stitches for width. What should be the minimum trace spacing in FPC? The minimum trace spacing required in FPC with 1 ounce copper is 4 mils. 40625 ≈ 9 floor joists. This technique enables the shortest return path with the least impedance for multiple layers and minimizes the return loop area. Here are the steps I took to try and solve this:I just created a board with a double-sided ground plane and would like to automatically via-stitch both sides. Several online tools can calculate the required trace width to carry rated current while keeping the trace temperature below a specified limit. Stitching ViasFor an example of stitching vias, see Figure 11. 1 Differential Signal Spacing To minimize crosstalk in high-speed interface implementations, the spacing between the signal pairs must be a minimum of 5 times the width of the trace. In this case, 3 and 2. Enter the number of inches (or centimeters) you are measuring on your gauge swatch. For example, a 30 ps rise/fall time results in 0. Maybe a bit clearer in the example if I had said that there will be, on one of the two sides to be joined at the finger joint, fourteen fingers and thirteen slots and on the other side there will be fourteen slots and thirteen slots. The design of an RF/high-speed via transition requires. At PCB Trace Technologies Inc . Getting hot spots on one side could cause warping. In a controlled impedance design, the selection of the materials used in the layer stackup is very important. Does the frequency actually relates to the fencing/stitching space, or placing the vias closer than the smallest λ/20 (for fencing) and λ/8 (for stitching) is all that matters? The frequency and the wavelength are intimately related, so the operating frequency has just as much to do with the via spacing as the wavelength does. For example, if you have 115 stitches and you need to increase 8 stitches, you'd divide 115 by 8: 115. Or you could layout some shorter spaces, (3-4-3-4-3-4-3-3-3). For both run and triple-run stitches, stitch length can be adjusted via Object Properties to suit the shape. Here you will find calculators and charts to help with yardage and dimensions of circle, flare, and pleated skirts, You will be able to determine fabric based on waist circumference, waist height, depth and number of. Serves to electrically bond the two areas. 0001) but was statistically similar to the 3. For other types of PCBs, like flex or HDI design, we have different standards on annular rings that might be used to calculate via size. Adjust stitch length for smoother or sharper curves. Contour is a curved fill stitch type – stitches follow the contours of a shape, creating a curved, light and shade effect. By default, you will have two copper layers. Using the same center point, replace the project onto the machine with the circular sewing attachment still in position. Critical Signals (continued) Signal Name Description HDMI_DATA1x High-Definition Multimedia Interface (HDMI) differential data pair, positive or negativeLlinares et al. 5 mm dia pads under, or immediately around, the drain of the transistor. The average suture spacing for LAP, RAS, and STAR was 2. 2E-6 Ohm-cm. Confining signal using stitching vias on a 2 layer PCB. It works for ground vias as well. Continue this process until you’ve go all the way around the edge. Stitching Vias 3 High-Speed Differential Signal Routing 3. The effect on EM1 of stitching multiple ground planes together along the periphery of multi-layer PCB stacks is studied. The ground vias (yellow circles) are spaced at about 250 mils on average. Bead Length = 2. We will assume. Selecting the Layer Material. Trace connections should be as wide as possible to lower inductance. the connection goes straight from pad to plane rather than pad-trace-via-plane) You have to check whether your PCB house can do this though, and it may cost more (via will need to be plugged and plated over to provide a smooth. Turn the fabric over. 3163. 024 in internal conductors and 0. If we assume a via diameter of 10 mils, then the circumference of the via is 31. Once you know your maximum frequency of your PCB, we simply need to use this formula to calculate the spacing, where c is the speed of light, ε is the dielectric constant, and f our maximum frequency of interest: For example, at 2. 0 differential pairs spaced in close proximity. What is the formula for hooks? There’s no specific formula for hooks as they are typically spaced based on practical needs and aesthetics. 5 mm), and then place a row of vias on that grid. Download scientific diagram | Variations in via fencing density around the perimeter of the PCB: (a) no via fence, (b) 400 mil via spacing, (c) 100 mil via spacing, and (d) 20 mil via spacing. termination. This makes selecting the footprint easier sometimes. Flexible PCB/ Rigid-Flex PCB Calculator. The vias are there to prevent excitation of parallel-plate modes; excitation of parallel-plate modes could act as a coupled. 25cm recommended. There are no rules for this and you need to input more via in free space as much as possible. Zg = Rg + jωLg. 7. Adjust stitch density by setting a fixed spacing value, or let auto spacing calculate it for you. However, 23 x 8 + 8 increases = 192 and we need 194 stitches, so in this case you would need to add two extra increases. Rounding up to 12 GHz bandwidth, assume 3e11mm/sec speed of light through vacuum and a 4. For shielding along specific traces that contain high-frequencies in their signal, the more the merrier. Use Edit Objects / Select > Reshape to reshape an object outline, edit stitch angles, or adjust entry and exit points. 6 GHz bandwidth. Do NOT backstitch at the beginning or. 75:1. So if I have N grids I can plot N subplots showing all. 35 ÷ 0. Later Rolled Up to create Sealed Line. Increase evenly across a row (balanced increase): k7, (m1, k14) repeat 3 times, m1, k7. The mouse bite hole sizes and spacings appear random to minimize the cleanup required after the board is. In the scheme of things, this is close enough! So the decreases will be done every 7 stitches across. As discussed above, via stitching is used for different applications like thermal management, EMI shielding, and power/ground net distribution. Lets say the joint is 30" long. The set can be removed by running the Tools » Via Stitching » Remove Via Stitching Group command, then clicking on any via in the group. If that is closer than you want, then you can remove one more stitch and add 2 MM of space to either side. Table 1-1. Design curves and an empirical equation are extracted from a. Quick answer: If you already know which PCB fab will make your boards, use their "preferred minimum hole size" for your vias. I am looking to reduce a continuous weld to a stitch weld to prevent warping during fabrication. Stitch this flat. However, you want to increase your stitch length to its maximum. For example, in the 2 via-hole case, when λ/2=46mm (via spacing) and eff ≈ 3. This method, which introduced a via-stitch guard trace in between. , crocus bulbs). The knowledge and design rules can be obtained by performing 3D analysis to signal vias with stitching. Good design should ensure an unbroken ground plane for the signal “return” - so no crossing lines - but this is often unavoidable, which can cause interference between sensitive components - eg your analog and digital parts, or high frequency parts. Even at 10 times the clock frequency (320 MHz) the wavelength is 0. The row of more densely distributed vias along the top edge of the board is the applied antenna ground and is required to maximize the RF performance of the device. Added a parallel resistor calculator to the Ohms Law tab. Another important use of vias is thermal. Version 7. 4 mm to . (Sorry for the math. The goal for PCB layout is to minimize the circuit loop area. That's a lotta seam in a New York minute! Metric. For most hand stitching, 6-8 spi looks good with 138 - 207 thread. 1,305. Note that vias are made out of plated copper which typically has a resistivity of 1. Dimensions from the connector or connector accessories to start of harness tie are given in Table 9-2. Note that vias are made out of plated copper which typically has a resistivity of 1. Information on the syntax and control of the calculation can be found in the document "Control, structure and syntax of calculations". The Trapunto effect automatically moves underlying travel runs to the edges of an object so that they can’t be seen. 1, No. 54mm for High speed) - Vias GND for free space is 5mm (5. Flower spacing varies based on the type of flower and its growth habits. 20 mm (Level B) Minimum hole size =. 30 millimeters. 00 (c)2006 IEEE 34 2. The real description of a via's impedance depends on a few important factors, and these are generally totally ignored in via impedance and propagation calculators: Pad size; Antipad size; Stitching via arrangement; Via hole diameter; At high frequencies, the capacitance becomes much more important and all via structures are. V8 adjusts the stippling every time. -The space of Vias GND for reduce EMI around the edge of PCB : 2. These important design features are incorporated into your design rules, making impedance-controlled routing quick and easy. 1,305. 1, No. Simple - Via Style(Hole size and diameter) is the. 20 mm (Level B) Minimum hole size = Maximum lead. 6 - Restore all polygons (t + g + e) and repour all (t + g + a) Here is the result: Share. Clicking this button will load the Preferred rule settings. 35 ÷ 0. Version 7. On our example FR-4 PCB operating at 6 GHz, a wavelength may be calculated from the well known formula as, Where F = MHz, λ (wavelength) = meters, Er = 4. Larger aspect ratios of 1:1, or even as high as 2:1, can be fabricated, but they bring reliability. Specific spacing and impedance may be required for high-speed circuits to minimize crosstalk, coupling, and. Simple - Via Style(Hole size and diameter) is the same through all layers. Power bus noise induced EMI and radiation from the board edges is the major concern herein. 0-mm spacing suggested by the uniform suture plan (P = 0. Via stitching can improve the the mechanical stability of your board too. Viewed 12k times. The fields with a green Via stubs are the unused part of the via. 7. Running Measurements to of each member: 0, 600, 1200, 1800, 2400, 3000, 3600, 3950 Mark out. Via pads are donut-shaped pads that connect the vias to the top or the inner traces. The diagonal holes have less copper than the diameter of the vias. This prediction matches with the frequency of occurrence of S21 minima in Fig. For general plane stitching, try to keep the spacing shorter than ~1/20th of a wavelength of the highest frequency that could be on your traces. 78 decimal inches (~ 3 3/4"). If you're stuck with an end gap that's too small, or double end members, try Adjust Both Ends Equally to open and spread the gap to each end. Consequently, the integrity of the via-stitch spacing is not always maintained in board areas of high design density, and the EMI effectiveness of the approach is compromised. The EMI at 3 m for different via stitch spacing and layer thickness is modeled with the finite-difference time domain (FDTD) method. Based on the resulting bandwidth, calculate the quarter wavelength to determine the maximum ground stitching via spacing. EMI shielding techniques protect devices from electromagnetic fields, radiofrequency interferences, and electrostatic fields. Step 1: Marking Sewing Lines With a Stitch Groover. b = 2 mil externally, 1 mil internally. You should care about the. Stitch length varies slightly in Tatami fill to ensure that small stitches are not generated at the edges of the shape. To calculate the number of steps of a spiral staircase, we need to: Find the height between the two floors that need connecting, let's say 12 feet (or 144 inches). 1. But, with a stitch density of . Key takeaways: Arrange ground planes one dielectric away from signal and power planes. is a necessity of design, but it can lead to some unpleasant consequences in a PCB layout if improperly harnessed. That was necessary to miss the drag tubes and brackets in a few places. The EMI at 3 m for different via stitch spacing and layer thickness is modeled with the finite-difference time domain (FDTD) method. The differential pair impedance calculators you'll find online provide a good first estimate of the impedance you can expect for your particular geometry. The impedance of that middle section can actually look very reactive as the length of the spacing between the grounding vias exceeds 1/8th of a wavelength. There are several reasons why the designer may need to stitch two layers together using many vias. To have your start and stop point at even spacing from the end, divide the remaining 3 mm by 2, so you want to start and stop at 1. The use of copper pour and via stitching is sometimes framed as an always-never type of decision, and with a variety of explanations to justify its use or omission. And that extra 0,5mm will hardly be noticeable. Either the desired impedance at a specific frequency is used to determine the waveguide width, or the width is entered and the impedance is calculated. In addition to the internal ground planes, I want to fill the signal layers with copper, and have vias between the pairs to serve as ground stitching and fencing. Nested shields prevent interference between different components. Abbreviations. They are: Blind via. What is the best spacing for coat hooks? A common estimate for coat hooks spacing is around 12 to 18 inches apart, but this can vary based on personal preference and available space. Fill Types To adjust the fill type of an object, right-click on the object, select Object Properties, then the Fill Stitch tab. He focuses specifically on their uses, as well as. Flush mount: in a standard mount, the last tread is one step below the floor level. This is based on the IEEE paper "Modeling Via Grounds in Microstrip" IEEE Microwave and Guided Wave Letters, Vol. Click Board Setup at the top. Click on the bottom left of the area and select “Place Origin. spacing d be at least greater than one via diameter to ensure. The guidelines above should inform your PCB via size determinations in order for. We used ½” spacing yet again, 1″ in from the raw edge. 4 (for typical FR-4 PCB material [6]). Anti-pads are the circular clearances in each power or ground layer that prevent electrical short to the plane. I have tried to follow the manufacturers recommendation for layout. Landing: a platform connecting two flights of stairs. Like they say, you can never have too many ground pins. 08mm ( 2. • Via pad size should be 25 mils or less and a finished hole size of 14 mils or less • Provide GND stitch to improve signal impedance transition • Location of via should be simulated. 16 proposed a procedure to calculate loop length in interlock fabrics and 1 × 1 rib 17 by means of some mathematical models. A 3D view of a complex impedance controlled PCB in. Diameters. Later Rolled Up to create Sealed Line. In addition, not all SERDES signal need to have. To sum up: 1) How much space there. through a specific thermal path, it is often possible to use calculators or simplified approaches during the system design phase. , we use via stitching mainly for: Allowing Higher Current Flow. Control, structure and syntax of calculations. 65, and 3. The calculator has options for the edge rate, dielectric constant, and also the height between the layers to determine the constraint values. 0. Placing many vias can help reduce this effect around a crossing line, or you can take. 05 ± 0. The restrictions posed by the PCB trace current capacity are critically important when it comes to PCB design. )Flat Stripline Using PCB Techniques right after WWII. It should be about 3mm wide on a 1. There are many tools available to calculate the trace impedance on high speed traces. In a flush mount, it is at. For example, at 2. There are a few different types of microvias. Figure 11. This information for example, is useful when designing. 7E-6 to 2. kind of accordian like thing, that you spread out and marked where your buttonholes should be but with knitting, that doesn’t work so well. For Tatami fill, stitch density is determined by row spacing. For quilt piecing use a shorter stitch length of 1. Provide starting and ending stitch counts, a total number of rows, and the number of stitches added or removed on each shaping row. Then, remove the project from the machine and pull the top threads to the back. Enter a number. com Figure 1: A section of a 1-GHz PLL synthesizer used in a 1-GHz receiver. It can be used with Circle or Digitize Blocks input tools. Stitch weld spacing formula. The differential pairs need to be routed symmetrically. In Layers, you can custom your layer set. An active component can act like a powerful heat source in your board, ultimately determining the equilibrium temperature in your PCB. Via stitching is usually more about high speed than DC when done at a board level like this. Drag the Centers or Total Length slider to see the effect of double end members. Spacing Calculations Take the result of the calculator divided by 20 to get RF trace via fencing max distance. Leverages DFA spacing table. 3). 6, you can clearly see the fabric between the stitches. Calculate number of copper layers needed – 2 layer, 4 layer, 6 layer etc. 3 in 12, you still have 12 inches from center to center so you haven't changed anything by changing the length of the weld. Snap tie spacing for concrete walls varies based on factors like wall height and design specifications. If you have 186 stitches and you need to increase 8 stitches to a total stitch count of 194, you will have to increase at every 23rd stitch (186/8=23. The via length is the length of your pcb. Add 1 to this value and round up the answer to the next whole number: 7. The spacing of the vias used to create the edge guard is difficult to determine without extensive modeling. If using vias becomes inevitable, pad-to-via connections should be less than 10 mils in length. On transport airplanes, the upper and lower wing skins are so thick they are called "planks" and actually form the effective upper and lower spar caps of a box structure that spans the entire chord between leading edge and trailing edge, with a relatively small number of ribs to hold the planks apart and provide buckling resistance. I designed a very compact 4 layer PCB that has many PCIe 2. Enclosure-level solutions are often a last re-The 'Thermal Via Design Calculator' calculates the optimal design (size, spacing, distribution) for thermal plated through vias in a PCB thermal pad. A via fence, also called a picket fence, is a structure used in planar electronic circuit technologies to improve isolation between components which would otherwise be coupled by electromagnetic fields. altium. 90/14 is a special needle sized for top stitching; it has a larger eye to accommodate the thicker thread. On the next page is an image of the Constraint Value Calculator. !! They are close together, and at the source of heat. There are no rules for this and you need to input more via in free space as much as possible. Cite. Thus, it maintains a healthy ground return path obtaining low resistance in the ground plane. Stitch this flat. In fact, a primary purpose of vias is to complete circuits between. Adding Via Stitching for Multiple Traces Carrying Large Currents . Table 1-1. The differential trace width and air gap spacing between the two traces of the pair need to be elected to achieve the impedance target. Click here to enlarge image. Figure 2. This method maximizes space efficiency, improves airflow, and minimizes shading between plants. For example, in the 2 via-hole case, when λ/2=46mm (via spacing) and eff ≈ 3. 2 Width and spacing The coupling of the intra-pair differential signals and increased spacing to neighboring signals help to minimize harmful crosstalk impacts and ElectroMagnetic Interference (EMI) effects. The stitching Via Style can be configured manually or imported from the applicable Routing Via Style design rule by clicking the Load values from Routing Via Style Rule button. Advanced PCB; Flex / Rigid-Flex PCB; PCB Assembly . g. ) Use effective trace width and spacing tips Routing surface traces and vias are not separate activities. 16. Gravel cost 686. The stitching Via Style can be configured manually in the Add Stitching to Net dialog, or imported from the applicable Routing Via Style design rule by clicking the Load values from Routing Via Style Rule button. Then go back and create the hole using a chisel with only one tooth, keeping the top and the bottom of the diamond shape in line with the edges of the groove. 08 Updates & Additions: This is because, along the length of a through-hole via, the dielectric constant that determines signal propagation is an effective dielectric constant with value of ~14 when Dk = 4. 7. IPC-SM-782A: This is the original standard for land pattern and. Before you actually punch sewing holes in your leather you have to give yourself a guideline to show where the sewing holes are going to go. Drag the Centres or Total Length slider to see the effect of double end members. The Sierra Circuits Impedance Calculator uses the 2D numerical solution of Maxwell’s equations for PCB transmission lines. 24 RF / Microwave Design - Line Types and Impedance (Zo) Transmission Line History -)Two Coplanar Strips in 1936. needlebobbinbobbin stitching. There are three weld beads in this example. The higher the frequency, the shorter the wavelength, and the closer together the vias have to be. For taller walls, closer spacing is required, such as 4 to 6 inches for walls between 4 to 8 feet high. 33 sq ft. Stitch counters are available from A&E that make this measurement easier, however, you can place a ruler next to the seam and perform the same task. shielding, arrays can exist simultaneously within a design, and layout designers need to understand the situations that warrant each rather than adding unnecessary cost. 00 (c)2006 IEEE 342. In this tutorial I show you how to make perfectly spaced stitch patterns along irregular curves and how to match stitches perfectly along circular patterns. An additional method is to set the grid to the via spacing you would like (say 2. I doubt your prototype service will charge you extra. There are a few methods for doing this, and different methods are better for different kinds of leather. I read data from binary files into numpy arrays with np. 6 mm to 0. This tool helps in determining the current-carrying capacity in circuit boards. Power bus noise induced EM1 and radiation from the board edges is the major concern herein. 5") at each end, then use the 3-5 spacing between (4. Available To. etc. If you remove the islands, then they won't radiate at all - and you don't have to pay for vias or remember to stitch that area if you change the layout. Divide this height by 9 1/2 inches, which is the code requirement for the maximum tread rise height for spiral staircases, to get: 144 / 9. (rignt click over plane edge,-> properties and name NET as GND) 2º make Back Ground plane. Free essays, homework help, flashcards, research papers, book reports, term papers, history, science, politicsDifferential pair trace routing. Minimum-sized vias (0. 5". To add the impedance models, click on ⊕ under the impedance calculator section and provide the following details:. tors to the ground and power pin on top layer. Overlapping regions use the most conservative spacing value. 2 - Shelve all polygons (t + g + h) 3 - Assign the copied tracks on GND signal. Select a straight stitch and lengthen the stitch. All Inch inputs and dimensions are actual physical finished sizes (unless otherwise noted) ? Select output Fraction Precision, Decimal Inch or Metric mm. Stitch spacing is the distance in millimeters between two needle penetrations on the same side of a shape. Combination stitch consisting of a single-needle chainstitch (401) and a 2-thread Overedge stitch (503) that are formed simultaneously. However, specific recommendations may vary, so it’s essential to refer to the planting instructions provided for each flower variety to ensure proper. In addition to the characteristic impedance of a transmission line, the tool also calculates. $egingroup$ as explained in the DELETED ANSWER, at high enough frequencies the skin effect and surface roughness cause the foils to become serious dampeners of any stored energy, which prevents the buildup of standing waves. With a stitch density of . These solutions are seen as cheaper than other solutions, yet they tend to be less effective, and a designer may end up settling on an enclosure solution to solve the problem. This method helps to maintain a low impedance and short return loops. Use the calculator below to determine how to decrease evenly across your row or round of knitting. The most insane isolation spec I ever endured was 100 dB over a range of frequencies. A four-layer PCB with a GND-VCC-VCC-GND power bus Does the frequency actually relates to the fencing/stitching space, or placing the vias closer than the smallest λ/20 (for fencing) and λ/8 (for stitching) is all that matters? The frequency and the wavelength are intimately related, so the operating frequency has just as much to do with the via spacing as the wavelength does. KiCad Board setup Menu. Know when to use balanced vs unbalanced RF feed lines, and what the proper impedance matching is for the circuit you are using. Fold it again downward 4". Two variables are swept in the simulation: Via Diameter and PCB Height. How you configure stitching vias depends on what you want to achieve. Standard PCB Capabilities. With Exact Spacing, if the 2nd to last member runs into the end member, the 2 end members combine (double members). Line thickness . In this video I show you how to calculate the amount of stitching you'll need for a project in order to reduce the amount of thread wastage and most importan. spacing. I often do a 250mil offset grid for non-RF, non highspeed digital boards. We might layout longer welds (4. The calculator has options for the edge rate, dielectric constant, and also the height between the layers to determine the constraint values. The EMI at 3 meters for different via stitch spacing and layer thickness is modeled with FDTD modeling. There are many demands placed on PCB stackup design. For a two-sided board, the via can be drilled from the bottom side without disrupting the pad on the top layer. This calculator allows you to add the impedance model and compute the desired trace geometry and spacing for a target impedance. 5 - 77) 3 = 2567. 5mm) diameter. Blind vias span from a surface layer to an internal layer and terminate at a landing pad. Some very dense SMT boards require smaller vias. Skip the next space and pick up the next sequence of four stitches along the next four spaces. To create a more open fill, enter a larger value. If using a multi prong make sure you have at least one (two is better) prong in the last hole you punched. Via stitching on the PCB is where a large number of vias are used to connect copper areas on different layers together. Designers place multiple vias on multilayered PCBs as close together as possible, and these are known as stitched vias. I want to calculate what. 1º make Front Ground plane -> name it GND. -The space of Vias GND for reduce EMI around the edge of PCB : 2. Getting the Most Accurate Impedance Calculations. This is my first attempt to design a PCB. Clicking this button will load the Preferred rule settings. 77GHz is obtained. As soon as you enable this option the dialog will close and the cursor will change to a crosshair, ready to define the area - note. 5" = 118. Maximum Spacing and Edge Distance) "The longitudinal spacing of fasteners between elements consisting of a plate and a shape or two plates in continuous contact shall be as follows: (a) For painted members or unpainted members not subject to corrosion, the spacing shall not exceed 24 times the thickness of the thinner part or 12 in. In these scenarios, you don’t need to mark them as “via-in-pad” features using Sierra Circuits online quoting.